AMD Announces SSE5 Instruction Set

AMD today announced its new x86-instruction set to improve performance in everyday computing tasks and applications – SSE5. AMD’s new SSE5 instruction set aims to improve performance in high-performance computing, or HPC, multimedia and security applications.

The new SSE5 instructions are available to developers today, but will not make it into AMD products until next-generation Fusion architecture with Bulldozer CPU cores. AMD announced the new instructions long before it would make it into processors “to foster an industry dialogue and solicit feedback,” continuing with the company’s open collaboration philosophy.

AMD’s SSE5 includes the following new instructions:

• 3-Operand Instructions A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.
• Fused Multiply Accumulate The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.

Intel declined to comment on AMD’s new SSE5 instructions, nor revealed if the company plans to integrate the instructions in the future.

“We have no reason to talk about 2009 plans, theirs or ours. We love what we’re doing today with processors, instructions, chipsets and software tools,” Intel public relations manager Dan Snyder said. “We’ve already released new SSE4 instructions that we have shown to give huge benefit to video and multimedia, and is already available to ISVs with Penryn family samples.”

SSE4 extensions have already been spotted in the wild on leaked Intel Penryn processors. SSE4a, a subset of SSE4, will make an appearance on AMD’s Barcelona architecture, set to debut on September 10th, 2007.  AMD has not disclosed when or if it plans to roll out the full SSE4 extension package.

Expect AMD to release processors featuring SSE5 in 2009 with Bulldozer equipped processors such as Sandtiger.