AMD picked up big headlines the day before Intel’s Fall Developer Forum with the announcement of its upcoming tri-core processors.
AMD’s original release did not specify if this tri-core processor, code named Toliman, would be a totally new processor or merely a stripped-down version of the existing Agena core. The answer, it appears, is both.
In an embargoed corporate roadmap forwarded to Global Tech News, details of these new triple-core oddities came to light.
The first triple-core processor, Toliman, is essentially a core-disabled version of the Agena quad-core processor. It includes a full Agena package, including the 2MB of shared L3 cache, with one core disabled.
Toliman, which will eventually herald the AMD Phenom 8000-product name, is scheduled to launch in February 2008 with mass availability in March. AMD representatives, speaking on conditions of anonymity, confirmed the initial 2.4 GHz Phenom 8700 and 2.3 GHz Phenom 8600 tri-core processors will launch with a 95W thermal envelope.
In late 2008, AMD will shift almost all of its 65nm quad-core offerings to 45nm. AMD will then follow up these initial quad-core offerings with 45nm dual-core and triple-core processors in 2009.
The first of these 45nm tri-core processors, codenamed Heka, will launch with DDR2 and DDR3 support. However, AMD guidance also details that Heka will ship with two different varieties: one with a shared L3 cache, another without. All 45nm quad-core AMD processors incorporate shared L3 cache, with the exception of the Propus family processor.
AMD guidance goes on to state that all mainstream Phenom quad-core processors, both with shared L3 cache (Deneb) and without (Propus), shipped in 2009 will feature DDR3 exclusively. Heka, on the other hand, will feature a mix of DDR2 and DDR3 support.
Unfortunately the answers for tri-core only raise further questions. While Heka has a unique codename, it seems to be a combination of cut-down Deneb and Propus quad-core processors. The logical conclusion would be that Heka is merely excess or defective Deneb and Propus processors from the 2008 launch.
Yet AMD’s roadmap goes on to detail one more chip: Regor. Regor, which has always been described by AMD as a dual-core version of Deneb, will make its debut with variable shared L3 cache and a mix of DDR2 and DDR3 support. Could it be that Regor is a core-disabled version of Heka, which is already likely a core-disabled version of Deneb/Propus?
One AMD representative declined to comment on these 45nm processors, stating that 2009 processor launches and specifications are still “tentitive.”